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RangeMAXTM
INTEGRATED PRODUCTS
LX1688
MULTIPLE LAMP CCFL CONTROLLER
DESCRIPTION
KEY FEATURES
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The LX1688 is a fixed frequency, dual current/voltage mode, switching regulator that provides the control function for Cold Cathode Fluorescent Lighting (CCFL). This controller can be used to drive a single lamp, but is specifically designed for multiple lamp LCD panels. The IC can be configured as a master or slave and synchronize up to 12 controllers. The LX1688 includes highly integrated universal `PWM or DC' dim input that allows either a PWM or DC input to adjust brightness without requiring external conditioning, since a single external capacitor CPWM can be used to integrate a PWM input. Burst mode dimming is possible if the user supplies a low frequency PWM signal on the BRITE input and no CPWM capacitor is used. The controller utilizes Linfinity's patented direct drive fixed frequency topology and patented resonant lamp strike
generation technique. Safety and reliability features include a dual feedback control loop that permits regulation of maximum lamp strike voltage as well as lamp current. Regulating maximum lamp voltage permits the designer to provide for ample worst-case lamp strike voltage while conservatively limiting maximum open circuit voltage. In addition the controller features include auto shutdown for an open or broken lamp, and a lamp fault detection with a status reporting output. To improve design flexibility the IC includes the ability to select the polarity of both the chip enable and dim (BRITE) inputs. Also included is a switched VDD output of up to 10mA that will allow the user to power other circuitry that can be switched on and off with the inverters enable input. This preserves the micro power sleep mode with no additional components.
Provision to synchronize lamp current & frequency with other controllers Dimming with analog or digital (PWM) methods (>20:1) Programmable Fixed frequency Adjustable Power-up reset ENABLE/BRITE Polarity Selection Voltage limiting on step-up transformer secondary winding Open lamp timeout circuitry Switched VDD output (10mA) Micro-Amp Sleep Mode Operates with 3.3V to 5V Supply 100mA output drive capability
APPLICATIONS/BENEFITS
Desktop LCD Monitors Multiple lamp panels Low Ambient Light Displays High Efficiency Lower Cost than Conventional Buck/Royer Inverter Topologies Improved Lamp Strike Capability Improved Over-Voltage Control
IMPORTANT: For the most current data, consult MICROSEMI's website: http://www.microsemi.com
PRODUCT HIGHLIGHT
D IM M IN G (B R IT E ) ENABLE
LAM PS
FETS
PHASE SYNC
RAMP RESET
IN P U T CO NNECTO R
12 13
LX1688 MASTER
24
S T R IK E STATUS FAULT 1 FAULT 1 FAULT 2 ENABLE B R IT E
125 Hz 5% Duty cycle Burst 65KHz run frequency
FETS
12 13
LX1688 SLAVE
24
LX1688 LX1688
VDD FAULT 2
S T R IK E STATUS
Ch3
10.0mV
Ch2
10.0mV
M 100s
Simplified quad lamp inverter showing synchronized output waveforms PACKAGE ORDER INFO
TJ (C) MIN VDD MAX VDD
PW
Plastic TSSOP 24-Pin
0 to 70 -40 to 85
Copyright 2001 Rev. 1.1a, 2003-03-21
3.0V 3.0V
5.5V 5.5V
LX1688CPW LX1688IPW
Page 1
Microsemi
Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAXTM
INTEGRATED PRODUCTS
LX1688
MULTIPLE LAMP CCFL CONTROLLER
ABSOLUTE MAXIMUM RATINGS Supply Voltage (VDD_P, VDD) ....................................................................... 6.5V Digital Inputs ..............................................................................-0.3V to VDD +0.5V Analog Inputs ............................................................................-0.1V to VDD +0.5V Digital Outputs .......................................................................... -0.3V to VDD +0.5V Analog Outputs ......................................................................... -0.1V to VDD +0.5V Operating Junction Temperature ..................................................................125C Storage Temperature ....................................................................................150C Lead Temperature (Soldering, 10 Seconds) .................................................300C
PACKAGE PIN OUT
AOUT VSS_P VSS BEPOL BRITE CPOR ENABLE I_R CPWM1 CPWM2 RMP_RST PHA_SYNC
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
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BOUT VDD_P VDD VDDSW TRI_C OLSNS ISNS ICOMP VCOMP VSNS SLAVE FAULT
Note 1: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal.
PWPACKAGE
(Top View)
THERMAL DATA
PW
Plastic TSSOP 24-Pin 100C/W
THERMAL RESISTANCE-JUNCTION TO AMBIENT, JA
Junction Temperature Calculation: TJ = TA + (PD x JC). The JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. FUNCTIONAL PIN DESCRIPTION
Pin Name AOUT VSS_P VSS BEPOL BRITE CPOR ENABLE I_R CPWM1 CPWM2
Description
Output Driver A Connects to dedicated GND for Aout and Bout Drivers Connects to analog GND Tri-mode input pin to control the polarity of the ENABLE and BRITE signal Analog/PWM input for brightness control Connects an external capacitor CPOR to VDD and is used for setting power-up reset pulse width. Used to enable or disable the chip Connects to external resistor RI; for bias current setting for internal oscillator Connects to external capacitor CPWM, used for integrating an external digital PWM signal for analog dimming Connects to external capacitor CPWM, used for integrating an external digital PWM signal for analog dimming. If SLAVE = "0", RMP_RST is a CMOS output; if SLAVE = "1", it is a CMOS input that locks the ramp oscillation frequency to the master clock If SLAVE= "0", PHA_SYNC is a CMOS output; if SLAVE = "1", it is a CMOS input that make the AOUT/BOUT phase synchronous with the master
Pin Name BOUT VDD_P VDD VDDSW TRI_C OLSNS ISNS ICOMP VCOMP VSNS
Description
Output Driver B Connects to dedicated VDD for Aout and Bout Drivers Connects to analog VDD Switchable VDD output controlled by ENABLE Connects to external capacitor CTRI Analog input to detect open-lamp condition Analog input from lamp current, has built-in 300mv offset Current error Amp's output; connects to external capacitor CICOMP Voltage error Amp's output; connects to external capacitor CVCOMP, can be used for soft-start Analog input voltage from transformer output
PACKAGE DATA PACKAGE DATA
RMP_RST
SLAVE
Input control pin for setting the IC either in Master or Slave mode; "1" for slave mode and "0" for master mode. Digital output to indicate maximum number of lamp striking attempts has occurred without lamp ignition.
PHA_SYNC
FAULT
Copyright 2001 Rev. 1.1a, 2003-03-21
Microsemi
Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 2
RangeMAXTM
INTEGRATED PRODUCTS
LX1688
MULTIPLE LAMP CCFL CONTROLLER
RECOMMENDED OPERATING CONDITIONS
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Parameter
Supply Voltage (VDD ,VDDP) BRITE Linear DC Voltage Range BRITE PWM Logic Signal Voltage Range Digital Inputs (SLAVE, PHA_SYNC, RMP_RST, BEPOL, ENABLE )
Min
3 1 0 0
LX1688 Typ
Max
5.5 2.5 VDD VDD
Units
V V V V
ELECTRICAL CHARACTERISTICS
O
Unless otherwise specified, specifications apply over the range: TA=-40 to 85 C, VDD (For LX1688IWP) & TA= 0 to 70 C, VDD (For LX1688CWP), VDD_P = 3.0 to 5.5V. RI = 80Kohms, CTRI = 0.083F
O
Parameter
Dimmer Conventional Dimming BRITE Input Voltage Reverse Dimming BRITE Input Voltage Max Brightness VBRT Voltage Full-darkness VBRT voltage ISNS input threshold voltage ISNS input threshold voltage BRITE-to-ICOMP propagation delay Strike and Ramp Generator Max. number of strike before fault Triangular Wave Generator Analog Output Peak Voltage Triangular Wave Generator Analog Output Valley Voltage Triangular Wave Generator Oscillation Frequency Max. Lamp Strike Frequency Lamp Run Frequency Lamp Run Frequency Lamp Run Frequency regulation over VDD OLSNS threshold voltage OLSNS hysteresis OLSNS-to-ICOMP propagation delay Fault, PHA_SYNC, RMP_RST, logic high threshold Fault, PHA_SYNC, RMP_RST, logic low threshold Minimum Fault-pin output current
Symbol
VBRITE_MAX VBRITE_MIN VBRITE_MAX VBRITE_MIN VBRT_FULL VBRT_DARK VTH_IAMP VTH_IAMP TD_BRITE NFAULT VP_TRI VV_TRI F_TRI FMAX_STK FLAMP FLAMP FLAMP_REG VTH_OLSNS VH_OLSNS TD_OLSNS VH VL I_FAULT
Test Conditions
VBEPOL = VDD VBEPOL = VDD VBEPOL = VSS or float VBEPOL = VSS or float VBEPOL = VSS, VBRITE = 0.4V VBEPOL = VSS, VBRITE = 2.6V TA= 0 to 70 C TA=-40 to 85 C
O O
Min
2.6 0.4 0.4 2.6 1.90 150 150
LX1688 Typ.
2.5 0.5 0.5 2.5 2.0 0 300 300 2
Max
Units
V
V 2.05 0.05 450 550 V V mV mV S
63 2.3 0.15 7 FMAX_STK = FLAMP X ~2.5 VOLSNS > 0.65V; VDD=5V O TA= 0 to 70 C VOLSNS > 0.65V; VDD=5V O TA=-40 to 85 C VOLSNS > 0.65V 650 300 GBNT VDD - 0.5 0.7 10 15 1 150 60 57 2.5 0.3 10 195 65 65 4 800 400 70 70 6 840 500 1 2.6 0.40 13 V V Hz KHz KHz KHz % /V `mV `mV us V V `mA
ELECTRICALS ELECTRICALS
Conventional polarity means that the lamp brightness increases with increasing voltage on the BRITE pin. Reverse polarity means that brightness decreases with increasing voltage Guaranteed but not production tested
Copyright 2001 Rev. 1.1a, 2003-03-21
Microsemi
Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 3
RangeMAXTM
INTEGRATED PRODUCTS
LX1688
MULTIPLE LAMP CCFL CONTROLLER
ELECTRICAL CHARACTERISTICS (CONTINUED)
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Parameter
Strike and Ramp Generator (continued) Minimum PHA_SYNC-pin output current Minimum RMP_RST-pin output current Minimum A_SYNC output pulse duty-cycle Minimum A_SYNC input pulse duty-cycle Minimum RMP_RST output pulse duty-cycle Minimum RMP_RST input pulse duty-cycle Output Buffer Output Sink Current Output Source Current Output Sink Current Output Source Current Output Sink Current PWM VSNS threshold voltage VCOMP Discharge Current IAMP transconductance VAMP, IAMP output source current VAMP, IAMP output sink current ICOMP discharge current VAMP transconductance ICOMP-to-output propagation delay BIAS Voltage at Pin I_R Pin I_R max. source current Power-on Reset Pulse Width Minimum VDDSW sourcing Current VDDSW Off Current General Operating Current Output buffer operating current ENABLE logic threshold ENABLE threshold hysteresis Sleep-mode current (see table-1 for Pin ENABLE polarity)
Symbol
I_PHA_SYNC I_RMP_RST DO_ASYNC DI_ASYNC DO_RST DI_RST ISK_OUTBUF IS_OUTBUF ISK_OUTBUF IS_OUTBUF ISK_OUTBUF VTH_VSNS ID_VCOMP GM_IAMP IS_IAMP ISK_IAMP ID_ICOMP GM_ICMP TD_ICOMP V_IR IMAX_IR TPOR IMIN_VDDSW IOFF_VDDSW IDD IDD_P VTH_EN VTH_EN IDD_SLEEP IDD_SLEEP IDD_SLEEP IDD_SLEEP
Test Conditions
VSLAVE = 0V VSLAVE = 0V VSLAVE = 0V VSLAVE = VDD VSLAVE = 0V VSLAVE = VDD VAOUT, BOUT = 1V VDD = 5.5V VAOUT, BOUT = 4.5V VDD = 5.5V VAOUT, BOUT = 1V, VDD = 3V VAOUT, BOUT = 2V, VDD = 3V VAOUT, BOUT = 1V, VDD = 5.5V
Min
10 10 49 48 10 5
LX1688 Typ.
Max
Units
`mA mA
50 50 17
% % % %
100 100 50 50 100 1.2 1.25 4 200 75 75 10 200 500 1100 0.95 50 1.05 31 10 25 1 5.5 2 0.8 1.7 0.2 20 20 20 20 2.6 2.8 190 15 8 4 2.4 50 50 800 1.3 500
`mA `mA `mA `mA `mA V `mA mho A A `mA mho nS V A mS `mA A
ISNS = 0.2V VCOMP, ICOMP = 0 VCOMP, ICOMP =VDD VSNS = 0.1V
100
CPOR =.1uF (VDD - VDDSW ) < 0.2V VENABLE = 0.8V, VBEPOL = VDD VDDSW = 0V VDD = VDD_P = 5V VOLSNS = VDD = VDD_P = 5V, CA = CB = 1000pF
mA mA V V
ELECTRICALS ELECTRICALS
VDD_P Leakage in Sleep Mode UVLO threshold UVLO hysteresis Copyright 2001 Rev. 1.1a, 2003-03-21
VTH_UVLO VH_UVLO
VENABLE = 0.8V (VBEPOL = VDD or float) VENABLE = 2.5V (VBEPOL = VDD or float) VENABLE = 0.8V (VBEPOL = VSS) VENABLE = 2.5V (VBEPOL = VSS) Rising turn-on threshold Falling turn-off hysteresis
A 300 300 2.9 V mV
Microsemi
Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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RangeMAXTM
INTEGRATED PRODUCTS
LX1688
MULTIPLE LAMP CCFL CONTROLLER
CHARACTERISTIC CURVES Typical Operating Current (VDD)
6 5.5 VDD Input Current (mA)
ISNS Input Threshold (V)
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ISNS Input Threshold Voltage Vs Temperature
380 360
VDD=5.5V 5 4.5 VDD=3V 4 3.5 3 -40
340 320 300 280 260 240 220 200 180
VDD=5.5V
VDD=3V
-15
10 35 Temperature (C)
60
85
-40
-15
10
35
60
85
Temperature (C)
Output Frequency Vs Temperature
70 68 Output Frequency (KHz) UVLO Thresholds (V) 66 64 62 2.9 2.85
Under Voltage Lockout Vs Temperature
Turn On
VDD=5V
2.8 2.75 2.7 2.65 2.6 2.55 2.5
VDD=3V
60 58 56 -40 -15 10 35 60 85
Turn Off
-40
-15
10
35
60
85
T emperature (C)
Temperature (C)
I_R Voltage Vs Temperature VDD=V
1.010 1.008 1.006 I_R Voltage (V) 1.004 1.002 1.000
Power-on-Reset Pulse Width Vs Temperature VDD=5V
40
35
TPOR(mS)
30 25
20 0.998
CHARTS CHARTS
0.996 -40
-15
10 35 Temperature (C)
60
85
15 -40
-15
10 35 Temperature (C)
60
85
Copyright 2001 Rev. 1.1a, 2003-03-21
Microsemi
Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 5
RangeMAXTM
INTEGRATED PRODUCTS
LX1688
MULTIPLE LAMP CCFL CONTROLLER
TABLE 1
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Pin BEPOL VDD FLOAT VSS
ENABLE POLARITY + (HI = CHIP_ON, LOW = CHIP_OFF + (HI = CHIP_ON, LOW = CHIP_OFF) - (LOW = CHIP_ON, HI = CHIP_OFF)
DIMMING POLARITY* CONVENTIONAL REVERSE REVERSE
* Conventional polarity means that the lamp brightness increases with increasing voltage on the BRITE pin. Reverse polarity means that brightness decreases with increasing voltage
OPERATIONAL MODES Controller Mode Master Controller Operation Run Striking Fault Run Slave Striking Fault Input Pin: OLSNS > 0.6V < 0.2V X > 0.6V < 0.2V X Input Pin: SLAVE VSS VSS VSS VDD VDD VDD Output Pin: FAULT L L H L L H Pin: RMP_RST Output: FINT Output: FINT Output: FINT Input: FEXT Input: FEXT Input: FEXT Pin: A_SYNC Output: FINT / 2 Output: FINT / 2 Output: FINT / 2 Input: FEXT / 2 Input: FEXT / 2 Input: FEXT / 2 Lamp Frequency FINT / 2 Ramping up / down Off FEXT / 2 Ramping up / down Off
BLOCK DIAGRAM
ISNS VSNS
FEXT/2
ERROR AMP TFF R PWR_ GD PWR_ BD 1.25V VAMP PWR_ GD FAULT VOLTAGE COMPARATOR
VCOMP ICOMP
VDD_P
Q
PHA_SYNC
Q
A OUT
T
SLAVE RMP_RST
FINT
RAMP RUN GENERATOR STRIKE GENERATOR
PWR_BD FAULT
OUTPUT STEERING LOGIC
Q
B OUT VSS_P
FEXT
300mV
IAMP
CURRENT COMPARATOR
1V 200K
+ 100K 100K
1V
+ BRT 100K 0-2V 800mV 600mV
BRITE
2.5V
+ 0.5V
100K
IGNITE
OLSNS
CPW 1
BLOCK DIAGRAM BLOCK DIAGRAM
CPW 2 BEPOL
1M
1M
PWR_ BD VDD
6 BIT COUNTER
TRI WAVE GEN
TRI_C
POLARITY DECODE
BIAS GEN UVLO
PWR_GD FAULT
ENABLE VDDSW
TTL BUF
INTERNAL VDD
PWR_BD
TTL BUF
FAULT
VSS
VSS
VDD
I_R
CPOR
Copyright 2001 Rev. 1.1a, 2003-03-21
Microsemi
Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 6
RangeMAXTM
INTEGRATED PRODUCTS
LX1688
MULTIPLE LAMP CCFL CONTROLLER
DETAILED DESCRIPTION
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The LX1688 is a backlight controller specifically designed with a special feature set needed in multiple lamp desktop monitors, and other multiple lamp displays. While utilizing the same architecture as Linfinity's LX1686 controller it eliminates the synchronized digital dimming and adds, lamp `strike' count out timer, lamp fault status output, and external clock input/output that permits multiple controllers to synchronize their output current both in frequency and phase. Operation From 3.3V and/or 5.0V Input Supply The LX1688 is designed to operate and meet all specifications at 3.3V 10% to 5.0V 10%. The under voltage lockout is set at nominally 2.8V with a 190mV hysteresis. Master/Slave Clock Synchronization One or more controllers (up to 11) may be designated as slave controllers and receive ramp reset and phase synchronization from the designated master controller. This will allow up to 12 lamps (24 with two lamps in series/controller design) to all operate in phase and frequency synchronization. This is important to prevent random interference between lamps through unpredictably changing electric and magnetic fields that will inevitably link them. The LX1688 has two independent oscillators, one for lamp strike and one for the lamp run frequency. The strike oscillator ramps the operating frequency slowly up and down when the open lamp sense input (OLSNS) indicates the lamp is not ignited. During this lamp strike condition the operating frequency of each IC will vary up and down as needed to strike its lamp. The controller is so designed that the master controller clock remains at the pre-selected frequency for fully ignited lamps even while striking. Likewise the designated slave controller will not alter the frequency or phase of the master clock during its strike phase. Thus each controller will vary its frequency as needed to strike its lamp then it will synchronize to the master clock frequency and phase. The TRI_C wave generator (see Block Diagram) sets the rate of operating frequency variation during lamp strike. The TRI_C generator is connected to a 6-bit counter that times out after 63 cycles and then latches the FAULT output high if the OLSNS input indicates no lamp current is flowing. Even in the case of timeout fault the master controller clock will continue to provide synchronization to the slave controllers. When synchronizing more than one controller the Ramp Reset (RMP_RST), Phase Sync (PHA_SYNC),
Copyright 2001 Rev. 1.1a, 2003-03-21
and Slave Input/Output are used. RMP_RST and PHA_SYNC should be connected between all the controllers. The master controller should have its SLAVE pin connected to VSS (GND) and the slave controllers SLAVE input to VDD (High). BEPOL Input The BEPOL pin is a tri-mode input that controls the polarity of the ENABLE and BRITE input signals. Depending on the state of this pin (VDD, floating, or VSS) the controller can be set to allow active high enable with active high full brightness or active high or low enable with active low full brightness (see Table 1). BRITE Input (Dimming Input) The BRITE input is capable of accepting either a DC voltage (.5V to 2.5V) or a PWM digital signal that is clamped on chip (<.5V or >2.5V). A digital signal can either be passed unfiltered to effect pulse `digital' dimming or filtered with a capacitor to effect analog dimming with a digital PWM signal. Analog Dimming Methods: * Mechanical or digital potentiometer set to provide 1V to 2.5V on the wiper output. A filter cap from BRITE to signal ground is recommended. * D/A converter output directly connected to BRITE input. A R/C filter using a capacitor from the CPW1 input to ground for applications where the ADC output may contain noise sufficient to modulate the BRITE input. * A high frequency PWM digital logic pulse connected directly to the BRITE input. The Brightness (BRT, internal node) output will be sensitive only to the PWM duty cycle, and not to the PWM signal amplitude, so long as the amplitude exceeds 2.6V for a logic high (1) and is less than .4V for a logic (0). This pulse frequency will typically be between 1KHz and 100KHz and will not be synchronized with the LCD video frame rate. A capacitor (CPWM) between CPW1 and CPW2 will integrate the PWM signal for use by the controller. Digital Dimming Methods: * Low frequency PWM digital logic pulses connected directly to the BRITE input. As above the Brightness (BRT internal) will be sensitive only to the PWM duty cycle, and not to the PWM signal amplitude, so long as the amplitude exceeds 2.6V for a logic high (1) and is less than .4V for a logic (0). This pulse frequency will typically be in the range of 90-320Hz
DESCRIPTION DESCRIPTION
Microsemi
Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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RangeMAXTM
INTEGRATED PRODUCTS
LX1688
MULTIPLE LAMP CCFL CONTROLLER
DETAILED DESCRIPTION (CONTINUED)
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and may or may not be externally synchronized to the LCD video frame rate. It will directly gate the signal BRT. CPWM should not be used in this case. Fault Pin The fault pin is a digital output that indicates that the maximum numbers of strike attempts has occurred without lamp ignition. In this condition the FAULT pin will go active high with typically 20mA drive capability. Holding the OLSNS pin low (<200mV) will also force timeout and activate the FAULT pin. When used as a master, fault condition true does not inhibit master clock outputs PHA_SYNC and RMP_RST. I_R Pin The run mode frequency of the output is one half the internal ramp frequency, which is proportional to a bias current set by resistor RI of 80.6K. The output frequency
can thus be adjusted by varying the value of RI-R, the typical range from about 50K to 100K. Since there is some variation in the frequency due to change in the input supply (VDD) it is recommended that the value of RI-R be selected at the nominal input voltage. Sleep Mode (ENABLE Signal) and Switched VDD (VDDSW) Since the LX1688 can be used in portable battery operated systems, a very low power sleep mode is included. The IC will consume less than 10A quiescent current from both the VDD and VDD_P pins combined, when the ENABLE pin is deactivated. The polarity of the ENABLE pin is programmable by the BEPOL input (see table 1). In addition the controller provides a switched supply pin VDDSW this output supplies at least 10mA at VDD .2V for external circuitry. This output can be used to power additional circuitry that can be enabled with the controller.
BIAS & TIMING EQUATIONS Formula 1: Triangular Wave Generator Frequency, FTRI Formula 2: Lamp Frequency (AOUT's switching frequency), FLAMP
FTRI =
Formula 3:
1 [Hz] (25 x RI x CTRI )
Formula 4:
FLAMP =
1 [Hz] 200e-12 x RI
Minimum Current Error Amp Bandwidth, BWIEA_MIN
Minimum Voltage Error Amp Bandwidth, BWVEA_MIN
BWIEA_MIN =
Formula 5: Softstart time, TSS
0.000048 [Hz] CICOMP
Formula 6:
BWVEA_MIN =
0.000048 [Hz] CVCOMP
Minimum Power-on Reset Pulse Width, TMIN_POR
TSS = 4,500,000 x CVCOMP [sec]
TMIN_POR = 2.3e6 x CPOR [sec]
DESCRIPTION DESCRIPTION
Copyright 2001 Rev. 1.1a, 2003-03-21
Microsemi
Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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RangeMAXTM
INTEGRATED PRODUCTS
LX1688
MULTIPLE LAMP CCFL CONTROLLER
TYPICAL APPLICATION
CN1 VIN 2 GND 3 GND 4 5 VBRITE 6 RMP_RST 7 PHA_SYNC 8 ENABLE 9 10 VDDSW 1 VIN C1
10% 470nF 16V
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U2 RMP_RST PHA_SYNC VDDP R5 39
4
SI9945AEY 8 7 6 5 1 3
R4 39
2
1:75 5 3 2 4 1
T1
C13 0.1uF 50V C14 VDDP Q2 2.2PF
PCB
CN2 1 HV1 2 LV1
+
C12
BC847ALT1
Q1
BC847ALT1
220 25V
R8 100K R6
82
C15
2.2nF 50V 5% COG
16V 10% 470nF 2 Analog Ground must connect to power ground at this point only 3
C2
1
AOUT VSS_P VSS BEPOL BRITE CPOR ENABLE I_R CPWM1 CPWM2 RMP_RST
BOUT VDD_P VDD VDD_SW TRI_C OLSNS ISNS ICOMP VCOMP VSNS SLAVE
24 23 22
10K
D1 R7 3 BAW56
21
R2 47 VDD
220nF 16V 10%
VDD
4 5
VDDSW
20 C6 82nF 19 18 17 16 15 14 13
C5
C4
220nF 16V 10% 1K
VDD
1 2
D2
3 BAW56
10nF 16V C3 10%
6 7 8 9 10
16V 10%
R1
80.6K 1%
2.2nF 16V 5%
C8
16V 10% 100nF
C7
R9 R10
1M
R12
BAV99
C16
RMP_RST PHA_SYNC
11 12
4.7nF 16V 10% 10nF 16V 10% C11 10nF 16V 10%
C9
D3 3
21
2.74K 1%
3.3nF COG 50V 5%
C10
2.74K 1%
R11
PHA_SYNC FAULT
R3
OPTION
LED1
220
Figure 1- Schematic for LX1688 Inverter Module configured as a Master
APPLICATIONS APPLICATIONS
Copyright 2001 Rev. 1.1a, 2003-03-21
Microsemi
Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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RangeMAXTM
INTEGRATED PRODUCTS
LX1688
MULTIPLE LAMP CCFL CONTROLLER
APPLICATION INFORMATION
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Application example with LX1688 This section will highlight the features of LX1688 controller by showing a practical example. Three identical inverter modules are connected to each other and each module drives a single lamp. One module configured as a master and two others configured as slaves. A complete schematic hooked up a a master is given in Figure 1, the schematic provides all necessary functions such as high voltage feedback for regulation the peak lamp voltage, short-circuit protection, open lamp sensing and lamp current regulation needed for a typical application. The section follows with measurement waveforms and list of material of the actual modules. For more detail design procedure and circuit description please refer to application note (AN-13), which is available in Microsemi's web site. Input Voltage The LX1688 controller can operate at 3.3 to 5.0V 10%, in this application all modules were driven by the same power voltage (a constant 5.0V), which provides VDD for controllers, and input voltage for the power section. Notice that VDD feeds all analog signals and VDD_P feeds only the output driver stage, these two signals should be filtered separately (Figure 1). Setting lamp frequency The value of R1 determines magnitude of internal current sources that set timing parameters. Equation (2) gives the relationship between Lamp frequency (FLAMP) and (RI_R), R1 in schematic. For this application we choose R6=80.6 Kohm, which results to a lamp frequency at 62.0 KHz. Dimming The LX1688 includes highly integrated universal `PWM or DC' dim input that allows either a PWM or DC input without requiring external conditioning. In this application we choose Digital Dimming by applying a PWM signal to BRITE pin. All modules were driven by the same PWM signals, but notice that it is possible to dim each module quite separately. BEPOL pin has three different modes (see table 1), in this application it is connected to VDD which means active high enable with active high full brightness. The PWM signal can be varied in frequency between 48-320 HZ. No capacitor between CPWM1 and CPWM2 is necessary.
Copyright 2001 Rev. 1.1a, 2003-03-21
Setting Master/Slave configuration Simply connecting pin 14 to the ground for a master and to the VDD for a slave will do master and slave configuration. As shown in figure 2, module (A) configured as master and modules (B) and (C) configured as slaves. Synchronization of Frequency and Phase To synchronize the Lamp frequency and phase of all modules, it is required to connect the RMP_RST pin of all the modules together and connect PHA_SYNC pin of all the modules together. Layout consideration By designing the layout in a proper way we can reduce the overall noise and EMI for the module. The gate drivers for MOSFETs should have an independent loop that doesn't interface with the more sensitive analog control function, therefore LX1688 provides two power inputs with separate ground pins (analog/signal), VDD feeds all analog signals and VDD_P feeds only the output drivers, as shown in figure1 these two pins (pin 23, 24) are separated and filtered by R14, C2 and C7. The connection of two ground pins should be at only one point as shown in figure1. The power traces should be short and wide as possible and all periphery components such capacitors should be located as closed as possible to the controller. Oscilloscope Waveforms Pictures The following oscilloscope waveform pictures are taken from the actual circuits and will show the operation of the modules in different modes when three identical modules are synchronized, one as a master, and two others as slaves.
A APPLICATIONS
Microsemi
Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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RangeMAXTM
INTEGRATED PRODUCTS
LX1688
MULTIPLE LAMP CCFL CONTROLLER
TYPICAL SLAVE APPLICATIONS
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CN 1 VIN VIN GND GND
C1 470nF 16V 10%
VDDP
1 2 3 4 5 6 7 8 9 10
VBR ITE RM P _R ST P HA_SY NC
C2 470nF 16V 10%
1
AOU T VSS_P
BOU T VDD_P VDD VDD_SW T RI_ C OLSNS
24
2
23
3 ENA BLE VDD SW
R2 47
22
VDD
VSS
VDD VBRITE
5 4
21
VDDSW
C5 C6 C7 C8
BEPOL BRIT E
6
C4 220nF 16v 10%
20
19
C3 10nF 16V 10%
CPOR
7
18
ENABLE
8
ISNS
17
Power Output Section
I_R
R1 9 80.6K 1%
10
ICOMP VCOMP VSNS
14 16
C9 C10
CPW M1 CPW M2
15
C11
11
RM P_RST PHA-SYNC
12
RMP_RST PHA_SYNC
SLAVE FAUL T
13
R3 220
C5 : 220nF 16V 10% C6 : 82nF 16V 10% C7 : 100nF 16V 10% C8 : 2.2nF 50V 5% C9 : 4.7nF 16V 10% C10-11 : 10nF 16V 10%
Master
LED1
CN 1 VIN VIN GN D GN D
C1a 470nF 16V 10%
VDDP
CN 1 VIN VIN GN D GN D
C1b 470nF 16V 10%
VDDP
1 2 3 4 5 6 7 8 9 10
1 2 3
VBR ITE R M P _R ST P H A _SY NC
C2a 470nF 16V 10%
1
AO U T VSS_P
BO U T VDD_P VDD VDD_SW T RI_ C O LSNS
24
4 5
2
23
6
VBR ITE R M P _R ST P H A _SY NC
C2b 470nF 16V 10%
1
AO U T VSS_P
BO U T VDD_P VDD VDD_SW T RI_ C O LSNS
24
3 EN AB LE VD D SW
R2a 47
22
VDD
2
23
7 8
3 EN AB LE VD D SW
R2b 47
22
VDD
VSS
VDD VBRITE
5 4
21
VDDSW
C5a C6a C7a C8a
BEPO L BRIT E
6
C4a 220nF 16v 10%
9 10
VSS
VDD VBRITE
5 4
21
VDDSW
C5b C6b C7b C8b
BEPO L BRIT E
C4b 220nF 16v 10%
20
20
19
C3a 10nF 16V 10%
CPOR
7
18
ENABLE
8
ISNS
17
Power Output Section
6
19
C3b 10nF 16V 10%
CPOR
7
18
ENABLE
8
ISNS
17
Power Output Section
I_R
R1a 9 80.6K 1%
10
ICO MP VCO MP VSNS
14 16
C9a C10a
I_R
R1b 9 80.6K 1%
10
ICO MP VCO MP VSNS
14 16
C9b C10b
CPW M1 CPW M2
CPW M1 CPW M2
15
15
C11a
11
C11b
11
RMP_R ST
12
RMP_RST PHA_SYNC
SLAVE FAUL T
13
RMP_R ST
12
RMP_RST PHA_SYNC
SLAVE FAUL T
13
PH A-SYN C
PH A-SYN C
A APPLICATIONS
R3a 220 R13a 100K
VDDSW
R3b 220 R13b 100K
VDDSW
C5a: 220nF 16V 10% C6a: 82nF 16V 10% C7a: 100nF 16V 10% C8a: 2.2nF 50V 5% C9a: 4.7nF 16V 10% C10-11a: 10nF 16V 10%
Slave 1
LED1a
C5b: 220nF 16V 10% C6b: 82nF 16V 10% C7b: 100nF 16V 10% C8b: 2.2nF 50V 5% C9b: 4.7nF 16V 10% C10-11b: 10nF 16V 10%
Slave 2
LED1b
Figure 2- Schematic modules connected as a Master and Slaves
Copyright 2001 Rev. 1.1a, 2003-03-21
Microsemi
Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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RangeMAXTM
INTEGRATED PRODUCTS
LX1688
MULTIPLE LAMP CCFL CONTROLLER
APPLICATION INFORMATION (CONTINUED)
WWW .Microsemi .C OM
Multiple Lamp Sync The figure 3 shows the sync signals (PHA_SYNC and RMP_RST) timing relationship to Gate signal AOUT, for the master module. AOUT and PHA_SYNC running at the same frequency and RMP_RST signal has the twice frequency.
Strike Mode Every IC includes a separate strike controller that operates from the primary oscillator; therefore the strike controller is independent of the sync signals. The following oscilloscope waveform picture is taken when the master module is on striking mode and the salves are on running mode.
Figure 3- Sync signals-Timing relationship to AOUT
CH2= AOUT(Master), CH3=PHA_SYNC, CH4=RMP_RST
Figure 5- Master is in striking mode while slaves are in
running mode CH2= AOUT(Master), CH3=AOUT(Slave1), CH4=AOUT(Slave2)
Output Drivers The figure 4 shows the gate signals of the modules, which are operating, in running mode during digital dimming with 95% duty cycle. As shown all signals are synchronized. The difference between each signal's duty cycles is because each lamp has an independent control loop.
Figure 4- Output drivers of both Master
and Slaves. CH2=AOUT(Master), CH3=AOUT(Slave1), CH4=AOUT(Slave2)
APPLICATIONS APPLICATIONS
Copyright 2001 Rev. 1.1a, 2003-03-21
Microsemi
Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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INTEGRATED PRODUCTS
LX1688
MULTIPLE LAMP CCFL CONTROLLER
APPLICATION INFORMATION (CONTINUED)
WWW .Microsemi .C OM
Digital Dimming The following oscilloscope waveforms are showing gate signals of Master and slaves during digital dimming at 50% and 5% duty cycle.
Figure 6- Gate signals during digital dimming with 50%
Figure 7- Gate signals during digital dimming with 5% duty
duty cycle CH2= AOUT(Master), CH3=AOUT(Slave1), CH4=AOUT(Slave2)
cycle CH2= AOUT(Master), CH3=AOUT(Slave1), CH4=AOUT(Slave2)
Output currents Figure 8 shows the output current of master and slaves during digital dimming with 5% duty cycle. The lamp currents are operating in phase and frequency synchronization. This prevents random interface between controllers and reduces EMI.
Figure 8- Output current during
digital dimming with 5% duty cycle R1= out(Master) R2=Iout(Slave1) R3=Iout(Slave2) Lamp Current at 10mA/Div
APPLICATIONS APPLICATIONS
Copyright 2001 Rev. 1.1a, 2003-03-21
Microsemi
Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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RangeMAXTM
INTEGRATED PRODUCTS
LX1688
MULTIPLE LAMP CCFL CONTROLLER
LX1688 MODULE BOARD LIST OF MATERIAL
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Reference Designator
U1 U2 Q1, Q2 D1, D2 D3 LED1 R1 R2 R3 R4, R5 R6 R7 R8 R9 R10 R11, R12 C1, C2
C3 C4 C5 C6 C7 C8 C9 C10, C11 C12 C13 C14 C15 C16 T1 CN1 CN2
Part Description
Backlight Controller Dual N-Channel MOSFET NPN Transistor Dual Diode Dual Diode LED 80.6 K 1% 1/16 W 47 ohm 5% 1/8 W 220 ohm 5% 1/8 W 39 ohm 5% 1/16 W 82 ohm 5% 1/16 W 10 K 5% 1/16 W 100 K 5% 1/16 W 1 K 5% 1/16 W 1 M 5% 1/16 W 2.74 K 1% 1/16 W 470 nF 16V 10% X7R 1206 10 nF 16V 10% 0805 220 nF 16V 10% X7R 1206 220 nF 16V 20% 0805 82 nF 16V 10% X7R 0603 100 nF 16V 20% X7R 2.2 nF 50V 10% 4.7 nF 16V 10% X7R 10 nF 16V 10% X7R 220 uF Tantalum 7343 220 pF 2KV 5% COG 2.2 pF PCB 2.2nF 50V 5% COG 3.3 nF 50V 5% COG Low profile, High voltage xfmr, turns ratio 1:75 Connector, 10 pin Connector, 2 pin
Manufacture
Microsemi Siliconix Motorola Motorola Philips
Part Number
LX1688 Si9945AEY BC847ALT1 BAW56 BAV99
NOVACAP
AVX AVX AVX NOVACAP AVX AVX AVX NOVACAP AVX NOVACAP Microsemi Molex Molex
0805YC224MAT2A 0603YC823KAT2A 0603YC104MAT2A 0603B22K500NT 0603YC472KAT2A 0603YC103KAT2A 1206N221J202NT 08055A222JAT2A 0805N332J500NT SGE2645-1 53261-1090
L M LIST OF MATERIAL
Table 2- List of material for LX1688 inverter module
Copyright 2001 Rev. 1.1a, 2003-03-21
Microsemi
Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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RangeMAXTM
INTEGRATED PRODUCTS
LX1688
MULTIPLE LAMP CCFL CONTROLLER
PHYSICAL DIMENSIONS
WWW .Microsemi .C OM
PW
24-PIN THIN SMALL SHRINK OUTLINE (TSSOP)
321 E P
F D AH
SEATING PLANE
E
B
G
L
C
M
Dim A B C D E F G H L M P *LC
Note:
MILLIMETERS MIN MAX 0.85 0.95 0.19 0.30 0.09 0.20 7.70 7.90 4.30 4.50 0.65 BSC 0.05 0.15 - 1.10 0.50 0.75 0 8 6.4 BSC - 0.10
INCHES MIN MAX 0.033 0.037 0.007 0.012 0.0035 0.008 0.303 0.311 0.169 0.177 0.025 BSC 0.002 0.005 - .0433 0.020 0.030 0 8 0.252 BSC - 0.004
MECHANICALS MECHANICALS
1. Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006") on any side. Lead dimension shall not include solder coverage
PRODUCTION DATA - Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time.
Copyright 2001 Rev. 1.1a, 2003-03-21
Microsemi
Integrated Products, Power Management 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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